In a synchronous computer system, digital signals are transmitted from output registers through logic elements and wires, and received by input registers. The rate at which the digital signals can be transmitted and received is controlled by a system clock which generates clock signals having a fixed relationship with respect to the digital signals. The performance of the computer system has a direct correlation to the maximum rate at which the digital signals are transmitted and received as controlled by the system clock.
For the proper operation of the computer system, the system clock should guarantee that the digital signals are held stable in the output registers to meet the required setup and hold times of the input registers. The important features of the signaling path which determine a maximum possible clock rate (Cmax) are: a maximum time (Tmax) required to propagate the digital signals through the signaling path; a minimum time (Tmin) required to propagate the digital signals through the path; the input register setup time (Tsetup); and the input register hold time (Thold). Taking these features into consideration, the maximum possible clock rate can be determined by: EQU Cmax=Tmax+Tsetup+Thold-Tmin [1]
This formulation suggests that the clock rate can be maximized by minimizing the time required to propagate the digital signals through the signaling path or by reducing variations between the minimum and maximum delays encountered along the signaling path. In known technologies, the maximum time required to propagate the digital signals along the signaling path can only be minimized by reducing the size, expressed in terms of physical length of the signaling path, or the complexity of the logic elements along the signaling path. In most cases, reducing the maximum propagation delays below design limitations has proven to be physically impossible. This leaves the reduction in variations between the minimum and maximum delays .as the principle means to achieve a maximum possible clock rate to improve the overall performance of the computer system.
Variations between the minimum and maximum propagation delays are primarily due to a number of, sometimes uncontrollable, contributing factors. Wire lengths, clock skew, fabrication processes, environmental conditions, such as temperature and voltage, can all induce variable propagation delays. Currently, reduction in delay variations is achieved by forcing the electrical lengths of the signaling paths to be equivalent. Equal lengths of the signaling paths can also reduce variations due to fluctuations in temperature and voltage.
Further reduction in the delay variations is usually achieved by "binning." In binning, the components used to construct the signaling path are carefully tested and selected to more stringent timing requirements than the design requirements. This results in increased system costs due to the additional testing and selection. Binning also decreases component yield because the more stringent timing requirements select fewer components.
Therefore, it is desired that process, environmental, and load induced variations of signaling propagation delays be reduced to increase the rate at which digital signals can be transmitted and received along signaling paths. In addition, the decrease of these variations should be attained without substantially increasing the cost of the computer system.